1. Field of the Invention
The present invention relates to a digital communication system, and more particularly to a deinterleaving apparatus and method for a digital communication system which improve reliability against bust errors occurring in transmission environments and simplify implementations thereof.
2. Description of the Related Art
In general, multi-channel digital communication systems use the convolution code in order to eliminate random noise occurring upon transmissions. The convolution code is robust with respect to random noise, but weak on the bust error referring to errors clustered at a certain region. Accordingly, the multi-channel digital communication system converts data streams having bust errors into streams with random errors.
The existing interleaving schemes are mainly classified into the block interleaving scheme and the convolutional interleaving scheme. The convolutional interleaving scheme has difficulties in its implementation compared to the block interleaving scheme, but has an advantage of being implemented in one fourth of the memory size and a half of the total delay time, so that the convolutional interleaving scheme is mainly used in instruments with a large interleaving size.
The interleaver of the convolutional interleaving scheme (i.e., convolutional interleaver) is one that changes input data streams from a certain order to a random order by using an FIFO shift registers having different delay depths. The structures for the interleaver and deinterleaver of the convolutional interleaving scheme are shown in FIG. 1.
The convolutional interleaver 110 is provided with k branches and m-bit FIFO shift registers M. That is, the larger the FIFO shift registers M become, the more the interleaving characteristics are enhanced. The convolutional deinterleaver 120 has the opposite structure to the interleaver 110. By doing so, interleaved data are deinterleaved so that original data is restored.
The structure of a deinterleaver using such FIFO shift registers requires many logic gates, causing a problem of hardware size and complexity. As a technology developed to solve such a problem, the use of random access memories (RAMs) instead of the FIFO shift registers has been proposed.
The use of the random access memories prevents the hardware from becoming large, but it requires additional logic elements to control address generations and memory controls.
That is, in case of carrying out interleaving operations by use of the random access memories, a multi-channel digital broadcast system has a different delay depth for each channel, so that a receiver has to generate a different address according to the delay depth interleaved for each channel. In particular, enlarging interleaved delay depths for the improvement of digital broadcast quality brings out a problem of logic size and complicated implementation that generate an address for each channel.
Further, depending upon deinterleaving operation characteristics, void data of different sizes is attached ahead of valid data for each channel, in accordance with a different interleaved delay depth for each channel. Accordingly, a starting point of valid data by channel becomes asynchronous with a system, causing a problem of additionally implementing synchronization logic elements.
Such a conventional interleaver has a disadvantage that its size becomes large as its structure becomes complicated.